A conventional semiconductor device, such as a conventional flash memory, includes a large number of conventional memory cells in a memory region. Typically, a logic region at the periphery of the semiconductor device includes logic devices. For example, FIG. 1A depicts a side view of a portion of a conventional memory 10. The logic portion is not depicted in FIG. 1. The conventional memory 10 includes memory cells 20 and 30. The memory cells include gate stacks 25 and 35, respectively. The gate stack 25 includes a floating gate 22 and a control gate 24. The floating gate 22 and control gate 24 are typically made of polysilicon and are separated by an insulating layer 23. The floating gate is typically separated from the substrate 11 by a thin insulating film 21. Similarly, the gate stack 35 includes a floating gate 32 and a control gate 34. The floating gate 32 and control gate 34 are typically made of polysilicon and are separated by an insulating layer 33. The floating gate is typically separated from the substrate 11 by a thin insulating film 31. Spacers 26 and 28 and 36 and 38 are provided at the edges of the gate stacks 25 and 35, respectively. The memory cells 20 and 30 also share a common source 12. The memory cell 20 includes a drain 14, while the memory cell 30 includes a drain 16. The source 12 typically includes two implants, a first, double diffused implant ("DDI") and a second, moderately doped drain implant ("MDDI") implant. The drain typically includes only an MDDI implant. Between the source 12 and drains 14 and 16 are channel regions 27 and 37, respectively.
FIG. 1B depicts a plan view of the conventional memory 10. The top, control gates 24 and 34 are thus depicted. The floating gates 22 and 32, insulating layers 21 and 31 and insulating layers 23 and 33 lie below the control gates 24 and 34. The source 12 and drains 14 and 16 of the memory cells 20 and 30 are also depicted. In addition, the drains 14', 14", 16' and 16" and shared sources 12' and 12" of four other memory cells (not separately numbered) are also shown. Therefore, as can be seen in FIG. 1B, the gate stacks 20 and 30 may include multiple memory cells.
Also shown in FIG. 1B are field oxide regions 42, 44, 46, 48, 50 and 52. The field oxide regions 42, 44, 46, 48, 50 and 52 electrically insulate portions of the memory cells of the conventional memory 10. For example, the field oxide regions 42 and 48 separate drain 14 from drains 14' and 14". Similarly, the field oxide regions 46 and 52 separate drain 16 from drains 16' and 16". Although only the field oxide regions 42, 44, 46, 48, 50 and 52 that are uncovered are shown, field oxide typically exists under the control gates 24 and 34. As grown, the field oxide regions 42, 44 and 46 are connected beneath the control gates 24 and 34, forming a single continuous field oxide region. Similarly, the field oxide regions 48, 50 and 52 are connected beneath control gates 24 and 34. Furthermore, although field oxide regions 44 and 50 are shown, these field oxide regions may be removed during fabrication to allow the sources 12, 12' and 12" to be electrically connected. Alternate conventional methods electrically isolate the memory cells using trenches or buried bit lines. Consequently, any structure which isolates memory cells will be termed a field isolation region.
FIG. 2A depicts one conventional method 60 for providing the conventional memory 10. The gate stacks 25 and 35 which cross the field isolation regions 42, 44, 46, 48, 50, and 52 are provided, via step 62. The source and drain implants are then provided, via step 64. Typically the source implant includes a MDDI implant and a DDI implant, while the drain implant includes an MDDI implant. Typically, the DDI implant includes P at a concentration of approximately 1.times.10.sup.13 -5.times.10.sup.14 atoms/cm.sup.2 and As at a concentration of approximately 5.times.10.sup.14 -8.times.10.sup.15 atoms/cm.sup.2. For the DDI implant, the P or As are implanted at an energy of approximately twenty to one hundred kilo electron volts. The MDDI implant typically includes As at a concentration of approximately 5.times.10.sup.14 -8.times.10.sup.15 atoms/cm.sup.2. The drain implant also typically includes As at a concentration of approximately 5.times.10.sup.14 -8.times.10.sup.15 atoms/cm.sup.2.
A portion of each of the sources 12, 12' and 12" is desired to be under the gate to facilitate erasing through the source 12, 12' or 12". Thus, once the dopants are implanted in step 64, an anneal or oxidation is performed to drive the source dopants under the gates 22 and 32, via step 66. The sources 12, 12' and 12" extend under the edges of the gate stacks 25 and 35 because of step 66. The spacers 26, 28, 36 and 38 are then provided, via step 68. Step 68 typically includes depositing insulating layers and etching the layers to form the spacers. Thus, the memory cells 20 and 30 are completed.
FIG. 2B depicts a second conventional method 70 for providing the conventional memory 10. The gate stacks 25 and 35 which cross the field isolation regions 42, 44, 46, 48, 50, and 52 are provided, via step 72. The first source implant and the drain implant are then provided, via step 74. Typically the first source implant includes a MDDI implant and a DDI implant, while the drain implant includes an MDDI implant. Typically, the DDI implant includes P at a concentration of approximately 1.times.10.sup.13 -5.times.10.sup.14 atoms/cm.sup.2 and As at a concentration of approximately 5.times.10.sup.14 -8.times.10.sup.15 atoms/cm.sup.2. For the DDI implant, the P or As are implanted at an energy of approximately twenty to one hundred kilo electron volts. The drain implant typically includes As at a concentration of approximately 5.times.10.sup.14 -8.times.10.sup.15 atoms/cm.sup.2.
A portion of each of the sources 12, 12' and 12" is desired to be under the gate to facilitate erasure through the source 12, 12' or 12". Thus, once the dopants are implanted in step 74, an anneal or oxidation is performed to drive the dopants in the first source implant under the gates 22 and 32, via step 76. The sources 12, 12' and 12" extend under the edges of the gate stacks 25 and 35 because of step 76. The spacers 26, 28, 36 and 38 are then provided, via step 78. Step 78 typically includes depositing insulating layers and etching the layers to form the spacers. A self-aligned source ("SAS") etch is performed, via step 80. The SAS etch removes the field isolation regions 44 and 50 so that the source 12, 12' and 12" can be electrically coupled using another implant. In one version of the conventional method 70, the spacers are provided in step 78 before the SAS etch is performed in step 80. Such an order protects the edge of the gate stacks 25 and 35 from damage during the SAS etch performed in step 80. Once the SAS etch is performed, a second source implant and a source connection implant are provided, via step 82. The second source implant typically includes As.
Although the conventional memory 10 functions, one of ordinary skill in the art will readily recognize that as the memory cells 20 and 30 shrink in size, the memory cells 20 and 30 may suffer from short channel effects. It is desirable to decrease the size of conventional memory cells 20 and 30 in order to increase the density of memory cells 20 and 30 in the conventional memory 10. This may be accomplished by decreasing the length of the floating gates 22 and 32 and, therefore, the length of the gate stacks 25 and 35. However, as the lengths of the gate stacks 25 and 35 decrease, the length of the channels 27 and 37 decrease. As the source 12 and drain 14 of a conventional memory cell 20 become closer, short channel effects adversely affect the behavior of the memory cell 20. For example, short channel effects may cause the threshold voltage of the memory cell 20 or 30 to drop below a desired level, preventing the memory cell 20 or 30 from functioning reliably.
Furthermore, the conventional memory cells 20 and 30 also have shorter channels 27 and 37, respectively, than desired. Referring to FIGS. 1A, 2A and 2B, because of the anneal steps 66 and 76, the source 12 is driven under the gate 22 and 32. This is desired because the source 12 is used to erase the memory cells 20 and 30. The drains 14 and 16, however, are used in programming the memory cell. The drains 14 and 16 need not be driven as far under the gate 22 and 32, respectively. Furthermore, sharp drain junctions 14 and 16 are desirable for programming. However, the drains implants are also driven by the anneal steps 66 and 76. Therefore, as depicted in FIG. 1A, the implants for the drains 14 and 16 are driven under the gates 22 and 32. As a result, the channels 27 and 37 are further reduced in size. Thus, the memory cells 20 and 30 are more subject to short channel effects, especially at higher densities and small gate lengths.
Accordingly, what is needed is a system and method for providing the semiconductor device in which the short channel effects for a memory cell of a given size are reduced. The present invention addresses such a need.